The Best 3D Packaging: SoC vs SiP?

Posted by Rich Hueners on Fri, Sep 30, 2011 @ 10:09 AM

System in a packageManufacturers are constantly confronted with device integration challenges as consumers want electronics to be smaller, more easily portable and more multi-functional than ever. Engineers have answered the challenge with system-on-a-chip (SoC) and system-in-a-package (SiP) technologies as the most successful designs for 3D packaging. These solutions are being used in a variety of industries, including the computer, consumer, aerospace, military, and medical electronic industries. SoCs and SiPs can be accomplished with a hi-rel wire bonder or ball bonder.

System on a Chip
SoC technology was designed for applications requiring components to be implemented into a single integrated circuit, such as those applications requiring the lowest power, the lowest unit costs and the highest clock rates. This single chip can contain a variety of functions including digital, analog, mixed-signal, and RF. Advantages of a SoC design include a smaller footprint for space requirements, higher performance due to the increased number of circuits on the chip, greater system reliability, lower power requirements and a potentially lower cost for the end user.

System in a Package
SiP technology was designed for multiple advanced packaging applications requiring a fully functional, highly specialized module that can be easily integrated into a system. A SiP includes multiple integrated circuits enclosed in a single package or module. The die containing the integrated circuits may be stacked vertically on a substrate and connected SiP Chip Stacked MCMby wires bonded to the package. Alternatively, the die can be connected through flip chip technology, in which solder or gold ball bumps are used to join stacked chips together. Localizing functionality to a SiP module reduces the complexity and cost of the system board,
and removes this design burden from the system designer.

So Which Technology is Better?
The choice between SiP and SoC often creates a debate among RF designers because both approaches provide different advantages for different end-market applications. SiPs allow for relatively easy hetero-integration of analog and RF functionalities with digital CMOS, with possible cost and performance benefits. However, proper system partitioning at the design stage is key to obtaining the maximum value from a SiP. SoCs provide the lowest manufacturing cost, but design costs are often higher and time-to-market is generally slower. In the end, the anticipated unit volumes and target ASPs for the required system will decide the best 3D packaging design.

What's Your Opinion?
We'd like to hear from you! Use the comments field below to give your opinion on the premier design and process for hi-rel 3D packaging.

Jessica Sylvester
Marketing Communications
Palomar Technologies

Topics: RF Packaging, wire bonding, 8000 wire bonder, hi-rel wire bonds, 3D Packaging, RF devices