“If you are creating high value hermetically sealed devices, what are the consequences of experiencing high voids in the package seal ring?”
High levels of voids in the package seal ring may cause leak failures, which in turn can decrease the reliability and performance of your device. It may result in a short device lifetime and /or premature failure, or may cause some unforeseen damage to the end use product. For the best product performance and longevity, a void free seal is highly desirable.
So, how can we minimize voids in package seal ring?
First, recall that the keys to a void free seal are:
- The quality of raw materials used
- Impurities in the preforms
- Cleanliness of components
- Prebake time
- Outgassing of materials and/or organic epoxies inside the seal cavity.
SST’s systems create hermetically sealed MEMS packages, such as IR sensors, gyroscopes, bolometers and accelerometers. Packages are required to be hermetically sealed to protect from all types of environmental conditions. All packages must pass the Fine and Gross Bubble Test according to the MIL SPEC 883 Method 1014 to be considered hermetically sealed. A Fine Leak Test must be performed first prior to Gross Bubble Test per MIL SPEC.
High levels of voids are typically caused by contamination, improper metallization and insufficient weight (pressure) on a package between the lid and the package. A vacuum bake out reduces moisture levels in sealed packages along with a uniform and free float of weights to provide consistent weight distribution in the reduction of voids in the package seal ring.
High pressure in the seal ring increases pressure of the package seal ring upon thermal cycling or loading. This type of pressure in turn may cause the lid of the package to separate from the entire package itself. For reliability concerns, we cannot have high pressure in a sealed cavity for a solder lid seal process.
We can do the following typical profile changes:
- No high pressure at end of solder sealing.
- Changes in purges and vacuum prebake.
These above changes results in longer profile run times but may reduce void levels in the package seal ring. The below examples are standard x-ray images of voids in a solder seal ring vs. reduction of voids in a solder seal ring.
Use of materials and methods that have been proven by SST for over 40 years can help ensure your high value packages are void free and perform to your customers’ requirements.
Let SST help you determine the ultimate process recipe by contacting us at email@example.com.
Figure 1. a) White spots show the voids in the solder seal ring. b) X-ray images show a significant reduction of voids in solder seal ring, providing a reliable and durable package
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|Process Development||Graphite Machining||MEMS Packaging|
Adrienne D. Williams, Ph.D.
SST Vacuum Reflow Systems