The Journey to Full-Scale Semiconductor Packaging, Part 2: Process Optimization Challenges of Semiconductor Manufacturing

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The journey from concept to full-scale semiconductor packaging is often hindered by a number of different obstacles along the way including everything from diverse teams scattered across the world to simply not understanding how the manufacturing process of die bonding, wire bonding or vacuum reflow impacts the package design and vice versa. In this 3-part series, we will present the challenges faced from package design and prototyping, through process development and process optimization to ensure the device can indeed be manufactured with the desired throughput and quality.

In Part 2, we present process optimization challenges often faced throughout the manufacturing cycle moving from prototype to production. We will discuss the various approaches to optimizing throughput and creating consistency to improve yield. These methods will primarily focus on Palomar machine specifics and revolve around material presentation choice, equipment work envelope layout, process step sequencing, and parameter choices. After walking through some of the best practices for each process element, we step through some actual cases of process optimization.

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Journey to full scale semiconductor pkg part 2 Webinar


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